EP2S130F1508C3N 820mA Industrial Electronic Components

■ Dedicated differential and single-ended I/O buffers
■ 3.3-V, 64-bit, 66-MHz PCI compliance
■ 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■ Joint Test Action Group (JTAG) boundary-scan test (BST) support
■ On-chip driver series termination
■ On-chip parallel termination
■ On-chip termination for differential standards
■ Programmable pull-up during configuration

Each Stratix II device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2 SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O
standards.